;----------------------------------------------------------------- ; Phil's PIC 16F1829 Template v1.00 ;----------------------------------------------------------------- ; ; Example uses internal 32MHz oscillator. ; ; Simple counter / LED flash ~2Hz on pin18 (RA1) ; ;----------------------------------------------------------------- list p=16f1829 ; list directive to define processor #include ; processor specific variable definitions errorlevel -306 ; suppress page boundary warnings errorlevel -302 ; suppress bank 0 warnings errorlevel -303 ; suppress 'program word too large' warning from __config lines errorlevel -202 ; suppress 'argument out of range' warnings ;---------------------------------------------------------------- #define skipifzero btfss STATUS,Z ; macros #define skipifnotzero btfsc STATUS,Z #define skipifcarry btfss STATUS,C #define skipifnotcarry btfsc STATUS,C ;----------------------------------------------------------------- ; Set PIC's hardware fuses (oscillator selection etc) ;----------------------------------------------------------------- __CONFIG _CONFIG1, _FOSC_INTOSC & _WDTE_OFF &_PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_OFF &_CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF __CONFIG _CONFIG2, _WRT_OFF & _PLLEN_ON & _STVREN_OFF & _BORV_19 & _LVP_OFF ; Notes: ; When using LVP_ON (Low power programming mode allowed) the MCLR pin cannot be used as an input. ;----------------------------------------------------------------------------------- ; Fuse definitions for reference (included in .inc file, pasted here for reference) ;----------------------------------------------------------------------------------- ;_CONFIG1 EQU H'8007' ;_CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- ;_FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins ;_FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins ;_FOSC_HS EQU H'FFFA' ; HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins ;_FOSC_EXTRC EQU H'FFFB' ; EXTRC oscillator: External RC circuit connected to CLKIN pin ;_FOSC_INTOSC EQU H'FFFC' ; INTOSC oscillator: I/O function on CLKIN pin ;_FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pin ;_FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pin ;_FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode (4-32 MHz): device clock supplied to CLKIN pin ;_WDTE_OFF EQU H'FFE7' ; WDT disabled ;_WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register ;_WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep ;_WDTE_ON EQU H'FFFF' ; WDT enabled ;_PWRTE_ON EQU H'FFDF' ; PWRT enabled ;_PWRTE_OFF EQU H'FFFF' ; PWRT disabled ;_MCLRE_OFF EQU H'FFBF' ; MCLR/VPP pin function is digital input ;_MCLRE_ON EQU H'FFFF' ; MCLR/VPP pin function is MCLR ;_CP_ON EQU H'FF7F' ; Program memory code protection is enabled ;_CP_OFF EQU H'FFFF' ; Program memory code protection is disabled ;_CPD_ON EQU H'FEFF' ; Data memory code protection is enabled ;_CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled ;_BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled ;_BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the BORCON register ;_BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep ;_BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled ;_CLKOUTEN_ON EQU H'F7FF' ; CLKOUT function is enabled on the CLKOUT pin ;_CLKOUTEN_OFF EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin ;_IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled ;_IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled ;_FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled ;_FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- ;_WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control ;_WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control ;_WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control ;_WRT_OFF EQU H'FFFF' ; Write protection off ;_PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled ;_PLLEN_ON EQU H'FFFF' ; 4x PLL enabled ;_STVREN_OFF EQU H'FDFF' ; Stack Overflow or Underflow will not cause a Reset ;_STVREN_ON EQU H'FFFF' ; Stack Overflow or Underflow will cause a Reset ;_BORV_HI EQU H'FBFF' ; Brown-out Reset Voltage (Vbor), high trip point selected. ;_BORV_LO EQU H'FFFF' ; Brown-out Reset Voltage (Vbor), low trip point selected. ;_BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (Vbor), low trip point selected. ;_LVP_OFF EQU H'DFFF' ; High-voltage on MCLR/VPP must be used for programming ;_LVP_ON EQU H'FFFF' ; Low-voltage programming enabled ;------------------------------------------------------------------------------ ; PROJECT'S VARIABLE DEFINITIONS ;------------------------------------------------------------------------------ CBLOCK 0x20 ; Define GPR variable register locations counter1 ; User variables allocated contiguously counter2 ; counter3 ; ENDC sample_1 EQU 0x7D ; Some other sample user registers sample_2 EQU 0x7E ; sample_3 EQU 0x7F ; ;------------------------------------------------------------------------------ ; EEPROM INITIALIZATION ; The 16F1829 has 256 bytes of non-volatile EEPROM, starting at address 0xF000 ;------------------------------------------------------------------------------ DATAEE ORG 0xF000 DE "PHIL" ; Example: Place 'P' 'H' 'I' 'L' at address 0,1,2,3 ;------------------------------------------------------------------------------ ; RESET VECTOR ;------------------------------------------------------------------------------ ORG 0x0000 ; processor reset vector pagesel START GOTO START ; When using debug header, first inst. ; may be passed over by ICD2. ;------------------------------------------------------------------------------ ; INTERRUPT SERVICE ROUTINE ;------------------------------------------------------------------------------ ORG 0x0004 ;------------------------------------------------------------------------------ ; USER INTERRUPT SERVICE ROUTINE GOES HERE ;------------------------------------------------------------------------------ ; Note the 16F1829 family automatically handles context restoration for ; W, STATUS, BSR, FSR, and PCLATH. Shadow registers store these SFR values, and ; shadow registers may be modified since they are readable and writable for ; modification to the context restoration. RETFIE ; return from interrupt ;------------------------------------------------------------------------------ ; Set up PIC hardware. Note: Many of these defaults are the power-on ; / reset values and may be ommitted or replaced with CLRFs as apt). ;------------------------------------------------------------------------------ START banksel OSCCON ;select bank for OSCCON register movlw b'01110000' ;[7] = SPLLEN (if PLLEN is enabled in CONFIG word 2, bit 7 is ignored) movwf OSCCON ;[6:3] = IRCF (1110: 8/32 MHz), [1:0] = SCS (00: As determined by FOSC in CONFIG word 1) banksel ADCON0 ;select bank for ADCON registers movlw b'00000000' ;00 = disable ADCs movwf ADCON0 movlw b'00000000' movwf ADCON1 banksel CM1CON0 ;set bank for CMxCON controls movlw b'00000000' ;00 = disable comparitors movwf CM1CON0 movlw b'00000000' movwf CM1CON1 movlw b'00000000' movwf CM2CON0 movlw b'00000000' movwf CM2CON1 banksel PORTA ;initialize the IO port data movlw b'00000000' movwf PORTA movlw b'00000000' movwf PORTB movlw b'00000000' movwf PORTC banksel LATA movlw b'00000000' movwf LATA movlw b'00000000' movwf LATB movlw b'00000000' movwf LATC banksel ANSELA ;select bank for ANSEL registers movlw b'00000000' ;00 = digital IO movwf ANSELA movlw b'00000000' movwf ANSELB movlw b'00000000' movwf ANSELC banksel TRISA ;set bank for port TRIS tri-state control movlw b'00000000' movwf TRISA ;set port A data direction (0=output) movlw b'00000000' movwf TRISB ;set port B "" movlw b'00000000' movwf TRISC ;set port C "" banksel INLVLA ;set reg page for logic level control movlw b'00000000' movwf INLVLA ;set port A input logic level threshold movlw b'00000000' movwf INLVLB ;set port B "" movlw b'00000000' movwf INLVLC ;set port C "" banksel WPUA ;set reg page for weak pull up control movlw b'11111111' movwf WPUA ;set port A input weak pull up control: 1 = on movlw b'11111111' ;(if pin is an output, pull up is disabled). movwf WPUB ;set port B "" movlw b'11111111' movwf WPUC ;set port C "" banksel OPTION_REG movlw b'11111111' ;Option reg. Note: If bit 7 = 1, all weak pull-ups are disabled. ;-------------------------------------------------------------------------------------------- ; Now that the PIC H/W is set up, we can actually get on with doing what we need to do... ;-------------------------------------------------------------------------------------------- banksel PORTA clrf counter1 ;clear a 24 bit counter clrf counter2 clrf counter3 demo_loop clrw bsf STATUS,C addwfc counter1,f ;add 1 to 24 bit counter addwfc counter2,f addwfc counter3,f movfw counter1 ;copy the counter value to the ports. [7:0] = PortC, [15:8] = PortB, [23:16] = PortA movwf PORTC ;note: counter bits [23:22], [19], [11:8] wont be available as outputs movfw counter2 ;as the respective bits are not implemented in ports A and B movwf PORTB movfw counter3 movwf PORTA goto demo_loop ;********************************************************************************************* END ; directive 'end of program'